Design Example of Programmable Timer

By Alireza Haghdoost

This page initially created for sources and pictures referencing steps of Design of digital, from architecture to synthesis article.

In the article I was describe detail of each steps in practical example, beginning from design specification, architectural definition, coding, verification and synthesis. This example 5 is a design of a programmable timer. Timers are common design modules in almost all types of system. The design of the programmable timer begins with a design specification for its features and capabilities, then take account into architectural design and drawing flow diagrams for each operation modes of programmable timer. This example is citation of "Verilog Coding for logic synthesis" book.

Verilog design file includes :

Pro_timer_1.v : initial version of programmable timer description which have an snippet synthesis problem. It is a piece of Verilog code that looks correct and simulates correctly but will not synthesize.

Pro_timer_2.v : this is corrected version of programmable timer description that could synthesis without error.

Testbench_mode0.v : Testbench for verification of programmable counter in operation mode 0.

Testbench_mode1.v : Testbench for verification of programmable counter in operation mode 1.

Testbench_mode2.v : Testbench for verification of programmable counter in operation mode 2.

Pro_timer_3.v : Despite Pro_timer_2 is fully synthesizable but this version complete partitioning of programmable timer like architectural description.